Our Take
IBM has demonstrated a working prototype that solves the quantum-mechanics wall by building up instead of shrinking, but the company has not disclosed manufacturing temperatures or published independent benchmarks—so the real bottleneck is yield and reproducibility at scale.
Why it matters
The semiconductor industry has hit a physical limit with traditional transistor shrinking. IBM's vertical stacking approach offers a documented path forward that competitors (Intel, Samsung, TSMC, Imec) are also pursuing, making this the inflection point where chip roadmaps shift from planar to three-dimensional.
Do this week
Hardware procurement teams: monitor which foundry partners (TSMC, Samsung, Intel) commit to CFET (complementary field-effect transistor) production timelines in the next 18 months, as adoption will determine GPU and accelerator availability by 2027–2028.
IBM demonstrates stacked transistor architecture in working prototype
IBM announced a prototype chip using a two-layer vertical stacking architecture called nanostack. The chip contains approximately 100 billion transistors on an area the size of a fingernail, achieving twice the transistor density of IBM's 2021 state-of-the-art design (company-reported).
The architecture stacks two layers of complementary field-effect transistors (CFETs) on a single silicon wafer. Each layer consists of three nanosheets 15 atoms thick, spaced nine nanometers apart. Critically, IBM staggers the transistors in the second layer rather than stacking them directly on top of the first layer, which the company says simplifies interconnection.
IBM reports the design enables chips to perform up to 50% more work in the same time and consume up to 70% less energy compared to its previous state-of-the-art architecture (company-reported). Jay Gambetta, IBM Research director, called it "a meaningful leap forward" rather than an incremental step.
The nanostack approach builds on nanosheet technology, which chipmakers have used since around 2022. IBM will license the architecture to semiconductor manufacturers; the company expects deployment in GPUs, CPUs, and other chip types within a decade.
Moore's Law hits a wall; vertical stacking offers a documented workaround
For over 50 years, chipmakers have increased computational power by shrinking transistors to fit more onto a single wafer. That approach has reached a hard physical limit: transistors are now so small (a few dozen nanometers) that quantum mechanical effects begin to interfere with function. They cannot reliably shrink further.
Vertical stacking sidesteps this constraint by adding layers rather than reducing transistor size. Qing Cao, a materials science professor at the University of Illinois at Urbana-Champaign who was not involved in IBM's work, confirmed that IBM's staggered-layer design enables "more precise alignment of layers, which is important for performance because transistors are so tiny." Cao also noted that IBM demonstrated the approach "on a full wafer using a state-of-the-art manufacturing line," moving beyond laboratory proof-of-concept.
Competing chip manufacturers (Intel, Samsung, TSMC) and the research institute Imec in Belgium are investigating CFETs. However, IBM's method of constructing the second layer directly on the first, rather than bonding two independently fabricated layers (as AMD does with 3D V-Cache), may offer manufacturing advantages in precision and alignment.
Dan Hutcheson, vice chair of TechInsights, told MIT Tech Review that the approach "puts another 10, 15 years on the roadmap" for chip development.
Thermal management and yield remain unresolved engineering challenges
Two obstacles must be cleared before nanostack chips reach volume production.
First, yield. Manufacturing errors are inevitable; a certain percentage of chips fail at creation. Stacking layers compounds this problem: if either the top or bottom layer is defective, the entire chip fails. Higher defect rates directly reduce profitability, potentially making vertical stacking economically unviable unless yields improve dramatically.
Second, thermal management. Building each layer requires careful temperature control—processes must stay below 400 °C to avoid melting the connections to the layer below. IBM has solved this constraint in its prototype but has not disclosed its methods. Cao's research group has independently demonstrated a stacking method using junctionless transistors, which avoids the "doping" step (typically the hottest part of transistor fabrication), keeping temperatures below 200 °C. Cao believes this approach could scale more easily to additional tiers, though his work remains at the proof-of-principle stage.
Neither IBM nor any independent party has published a full manufacturing blueprint or yield data. The company's decision to partner with external manufacturers rather than fabricate chips itself signals that the technical path to production remains open and competitive.